1. Field of the Invention
The present invention relates to a semiconductor memory and in particular relates to a semiconductor memory wherein the layout area of the memory cells in a non-volatile semiconductor memory utilizing ferroelectric capacitors is reduced and unnecessary rewriting when reading is eliminated.
2. Description of the Related Art
A ferroelectric memory (FRAM) using ferroelectric capacitors for the memory cells is capable of holding information in a condition in which the power source is turned off and is capable of high-speed reading comparable with SRAM, and reading and writing with low power consumption. Such memories are therefore widely employed in IC cards, storage media of game equipment and tag ICs.
In a ferroelectric memory, data is stored by utilizing the polarizing effect of the ferroelectric capacitor. For example, when writing, data “0” is written by polarizing in the positive direction by applying a positive voltage to the ferroelectric capacitor and data “1” is written by polarizing in the negative direction by applying a negative voltage. When reading, a positive voltage is applied to the ferroelectric capacitor. If the capacitor has data “0”, its direction of polarization is not inverted; on the other hand, if the capacitor has data “1”, its direction of polarization is inverted. Accompanying this process, the potential of the bit line is made high level or low level (high level in the case of data “1” but low level in the case of data “0”) in accordance with the amount of charge that flows onto the bit line (a small amount of charge in the case of data “0” but a large amount of charge in the case of data “1”). In other words, in the reading operation, the presence of charge by polarization inversion is detected.
Since in the case of ferroelectric memory positive voltage is applied to the ferroelectric capacitor when reading, this process constitutes destructive reading. After reading has been performed, it is therefore necessary to rewrite this read data to the memory cells that have been read.
Ferroelectric memory may be of the 2 transistor/2 capacitor type, in which a memory cell comprises two transistors and two ferroelectric capacitors, or of the 1 transistor/1 capacitor type, in which a memory cell comprises one transistor and one ferroelectric capacitor. In the case of a 2 transistor/2 capacitor type, complementary data are recorded in the two capacitors and complementary signals are output to a bit line pair on reading, these complementary signals being detected by a sense amplifier. In the case of a 1 transistor/1 capacitor type, the data are recorded in a single capacitor and, on reading, high level or low level is output to the bit line and the sense amplifier detects the stored data by comparing the bit line level with a reference level that is generated by a reference memory cell. Although the circuit layout of the memory cells is simpler in the case of the 1 transistor/1 capacitor type, in the reading operation, it is necessary to perform a comparison with a reference level provided by a memory cell used for reference purposes.
Ferroelectric memories are described in for example Laid-open Japanese Patent Application No. 2002-133857 and Laid-open Japanese Patent Application No. 2003-197869 or IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 5, May 2002, “Bit line GND Sensing Technique for Low-voltage Operation FeRAM”. These documents all disclose ferroelectric memories of the 1 transistor/1 capacitor type (1T1C). Since the memory cell construction is simpler in the case of 1T1C ferroelectric memories, this type is more suitable for large capacity memories. However, since the potential of the bit line rises during reading in accordance with the data of the memory cell, the voltage between the plate line and the bit line is decreased, causing the voltage applied to the ferroelectric capacitor to fall and so decreasing the amount of polarization charge that flows out. This lowers the potential difference of the bit line and so lowers the reading margin.
Laid-open Japanese Patent Application No. 2002-133857 and IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, No. 5, May 2002, “Bit line GND Sensing Technique for Low-voltage Operation FeRAM” disclose a detection circuit that holds the bit line potential at ground level when reading, in order to prevent this lowering of the reading margin. By maintaining the bit line potential at ground level, the full-swing power source voltage can be applied to the ferroelectric capacitor, thereby preventing a lowering of the amount of polarization charge.
Laid-open Japanese Patent Application No. 2003-197869 also proposes an optimum layout in a 1T1C ferroelectric memory.